Semiconductor Engineering

Scalable End-To-End Test Solutions For Today’s Complex SoCs

Left-shifting DFT, scalable tests from manufacturing to the field, enabling system-level tests for in-field debug.
EDN

DFT Analyzer Validates Design-For-Test Features

Asset InterTech has announced its DFT Analyzer, which according to the company reduces manufacturing and test costs by validating the boundary-scan design-for-test features in a circuit-board design ...
Electronic Design

Design-For-Test The Smart Way: dFT With A "Big T" And A "Little d"

Design-for-test, or DFT, should facilitate high-quality test, not change the design. Test techniques and strategies need to supply a high-quality test that screens out defective devices, avoiding ...
Electronic Design

What’s Next for Physically Aware DFT?

Why isolated flows negatively impact design schedule and PPA. Benefits of unified DFT, synthesis, and physical design flows. Physical implementation optimization methods for test compression and scan ...
EDN

First STIL link between DFT and production test for SoC

Design-for-test (DFT) software maker Teseda (Portland, Oregon) and test-and-measurement house Agilent Technologies (Palo Alto, Calif.) announce a link that both companies claim will ensure, for the ...
Semiconductor Engineering

Making IC Test Faster And More Accessible: Part 1

The fundamental challenges of IC test have been the same for a long time. At the heart of all test strategies is controllability and observability. First, control the state of the chip with known test ...