The ability to control test cost while design sizes have grown exponentially is a success story that relies on the invention and continuous improvement of embedded test compression. One way test ...

Many styles of test interfaces have been optimized for various constraints and goals over the years. There does, however appear to be a trend of test moving toward standard interfaces and increased ...

As companies strive to achieve higher quality and reliability for their products, and as package sizes and the number of available pins continue to shrink, there is also a persistent need to keep test ...

Chip testing used to be straightforward. The development team used fault simulation to select a subset of the functional tests that could detect most possible manufacturing faults. These were ...

Although the term DigRF may lead to initial impressions of a digital signal somehow integrated into an RF signal path, this is not the case. DigRF is a published standard that describes a digital ...

This paper provides a complete solution to the GPIO Verification for any SoC. GPIO interface is available in every ASIC. To avoid duplicate efforts and (save) time to verify the GPIO interface, we ...