EDN

Reduced pin-count test

On test equipment and on boundary-scan and other DFT approaches, see: www.tmworld.com/ic and www.tmworld.com/dft. For Jay Jahangiri's elaboration on the need for ...
Semiconductor Engineering

Beyond The Bottleneck: 3 Breakthroughs In High-Throughput Connector Testing

In any production environment, testing components quickly and accurately is a dual challenge. A solution from Modus Test addresses this by combining an MPT tester with an MTC cycler —a setup that ...
EDN

TAP interface role expands in device test

Many styles of test interfaces have been optimized for various constraints and goals over the years. There does, however appear to be a trend of test moving toward standard interfaces and increased ...
Electronic Design

Low-pin-count test helps manage test cost

The ability to control test cost while design sizes have grown exponentially is a success story that relies on the invention and continuous improvement of embedded test compression. One way test ...
Electronic Design

Using ATE for Efficient DigRF Interface Testing

Although the term DigRF may lead to initial impressions of a digital signal somehow integrated into an RF signal path, this is not the case. DigRF is a published standard that describes a digital ...