EDN

Altera aids floating-point DSP implementation in FPGAs

Altera is quietly rolling out the ability for DSPdesigners to move directly from Simulink models to floating-point data pathsimplemented in Altera FPGAs. The capability, fully described by Altera ...
EDN

Enabling Impactful DSP Designs on FPGAs with Hardened Floating-Point Implementation

This paper discusses the evolution of floating-point digital signal processing (DSP) implementation in Altera® FPGAs, starting from the fused datapath design flow in previous-generation families to ...
Electronic Design

64-bit Floating Point Coprocessor Supports IEEE 754 Calculations

The uM-FPU64 floating point coprocessor chip provides support for IEEE 754-compatible, 64-bit floating point and integer calculations, expanded digital I/O, and analog input capabilities as well as ...