High performance clock buffers — those without phase-locked loops (PLLs) — are often used in communications designs for duplication, distribution and fanout of clock signals. Sensitivity to long-term ...

Microsemi Corporation expanded its communications timing portfolio with its first family of clock distribution differential fan-out buffers. The 28-part family of buffers supports clock rates of up to ...

High-speed communications require system designers to optimize clocking performance while adhering to both performance and cost-budget requirements. When selecting an optimal clock, the developer must ...

Fanout buffers and clock dividers are general-purpose clock building-block devices that can be used in many applications. They are ideal for clock and signal distribution in various systems, from ...

Clock distribution networks are critical components in modern integrated circuits, ensuring that the timing signal reaches every element with minimal delay and skew. As device geometries shrink and ...

This paper presents a simple but practically precise estimation of periodic single-tone power supply induced jitter (PSIJ) for MOS clock buffer chains. The estimation is algebraically simple for its ...

A fan-out buffer is used in timing applications that require multiple copies of a clock signal to be distributed. When choosing the right fan-out buffer for a timing application, it’s usually helpful ...

Silicon Laboratories has introduced the first universal clock buffers capable of replacing LVPECL, LVDS, CML, HCSL and LVCMOS buffers with a single ic, eliminating the need for multiple fixed format ...

PCIe has been around since 2004. It’s a high-speed serial computer expansion bus specification that replaces older PCI and PCI-X standards. PCIe currently supports the Generation 4 specification. In ...