- Productive: Designed for maximum engineering productivity and time-to-market acceleration for connecting semiconductor IP blocks and sub-systems for Arm and RISC-V-based designs, accelerating time ...

Arteris (NASDAQ:AIP) executives highlighted the company’s focus on on-chip and chiplet data movement, recent product launches, and an expanding security verification offering during a presentation at ...

Arteris (AIP) system IP facilitates the seamless integration of functional safety solutions in automotive systems. The ISO 26262 functional safety certification for Ncore cache coherent interconnect ...

As the number and variety of computing elements in SoCs grow, specific application areas require the tight connection of key processing elements through coherency. Ncore Interconnect IP from Arteris ...

CAMPBELL, Calif., Oct. 21, 2024 (GLOBE NEWSWIRE) -- Arteris, Inc. (AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, and SiFive, Inc., the gold standard for RISC-V ...

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To ...

A new technical paper titled “Learning Cache Coherence Traffic for NoC Routing Design” was published by researchers at Nanyang Technological University. “In this work, we propose a cache ...