Electronic Design

High-Density, Low-Power 32M CMOS SRAM

Alliance Memory today expands its line of legacy low-power CMOS SRAMs with a new 32M IC (2M x 16 / 4M x 8 switchable), the company's highest density low-power device to date. A line of legacy ...
Nature

Low-Power CMOS Transceivers and Power Amplifiers

The ongoing evolution of wireless communications has placed a premium on energy efficiency, particularly in applications such as the Internet of Things and short-range wireless systems. Low-power CMOS ...
EDN

110 nm Standard Cell CMOS Technology

The Fujitsu’s CS91 is 110 nm channel length standard cell product that is based on the CMOS process technology for high speed and low power System on a Chip (SoC). It has a standard cell library that ...
Nature

CMOS Technology for Neural Stimulation and Power Management

CMOS technology has become a fundamental enabler in the advancement of neural stimulation devices, combining the benefits of low-power operation with high-density integration, thus allowing for ...
EDN

3-D interconnect integrates CMOS ICs

Silicon bonding technology promises optimized density, power efficiency, and performance In conjunction with Raytheon Vision Systems, wafer-bonding-process developer Ziptronix (Morrisville, NC) has ...