Design-Reuse

Domino Logic in ASIC Design Flow - Detailed Methodology and Breakthroughs in High Speed Design Automation Approach

Geneva -- September 22,2008 - Engineers at STMicroelectronic have revealed how to use domino logic, a very fast circuit design style utilized in the highest performance custom designs,in an automated ...
EDN

Altera’s Structured ASIC design flow now ITAR-compliant for military apps

Altera Corporation has announced that the U.S. Department of State has certified that the company's HardCopy II structured ASIC design and manufacturing flow is compliant with International Trade in ...
EDN

Test engineers must join ASIC flow early

Paul Taubman is a senior design engineer for Tality Corp., Cadence Design Systems' services organization. In this article he shows how test engineers should interact with designers in order to ...
Electronic Design

FPGA Prototyping Tool Aligns With ASIC Flow

Over a third of all high-end ASIC designers now use FPGAs for prototyping 500,000-plus-gate designs. Driving this trend is the fact that a median application-specific integrated-circuit (ASIC) design ...
Design-Reuse

RISC-V Powered Executive M.Tech VLSI PG Program for Next-Gen Chip Designers

Maven Silicon has collaborated with PES University and launched a unique Executive MTech in VLSI Design, Blended Weekend Classroom Degree Program for working professionals in India. This advanced PG ...